This invention relates generally to digital-to-analog converters having an R-2R ladder network and more particularly, it relates to a digital-to-analog converter which employs an R-2R ladder network composed entirely of complementary metal-oxide-semiconductor (CMOS) transistors,
For use with digital-to-analog converters, R-2R ladder networks are generally known which are composed of equal-valued resistors R arranged in a uniform ladder array. Each section of the ladder array has a leg or rung of two "R" elements connected in series, and the connection between each ladder section has a single "R" element connected in series to the next ladder section. Another single "R" element is also connected between the last single "R" element and a ground potential so as to complete the ladder array. This type of arrangement provides for equal parallel "R" impedance at each node of the ladder array when going from the most significant bit (MSB) to the least significant bit (LSB). Thus, if the resistive elements are of a uniform resistance value a reference current applied to the input at the MSB end will divide equally at each ladder node so that the output current for each successive 2R ladder rung, and thus each bit will be one-half of the output current of the previous bit down to the LSB. The uniform resistance value and node current division thus implies that the voltage drop on each "R" element of the ladder array must decrease by one-half as well for each succeeding ladder section. Such a conventional arrangement is shown in FIG. 1 of the drawings.
In U.S. Pat. No. 4,336,527 to von Sichart et, al., there is disclosed a digital-to-analog converter utilizing an R-2R ladder network wherein all of the R elements of the networks are implemented by MOS transistors of a single polarity, i.e. either N-channel or P-channel, biased in the "triode" operating region. A major problem associated with the sole use of single-polarity MOS transistors is the non-linearity error induced by other coefficients of resistance of the MOS "R" elements when converting a digital input signal into an analog output signal. This is because the drain-to-source resistance of each element of the MOS R-2R ladder array is completely determined by each respective drain-to-source voltage, gate-to-source voltage, and source-to-substrate voltage. Since the voltage drop on each "R" element of such a ladder network changes from the MSB end to the LSB end, the resistance values of the individual MOS transistors will deviate from a theoretically uniform resistance value of R. Another problem encountered with the R-2R structure formed of single-polarity MOS transistors is that the non-linearity error induced by the voltage coefficient of resistance will change as the reference current is switched from positive to negative, causing full-scale symmetry error.
Another problem encountered with the R-2R circuit described by the von Sichart et. al. reference is that the use of asymmetrical drivers for each R-2R switching cell will induce a long settling time at the digital-to-analog output by permitting the output and ground switches of each cell to be momentarily and simultaneously off for the input logic transition of "0" to "1", and momentarily and simultaneously on for the input logic transition of "1" to "0". This momentary condition will cause current throughout the ladder array to divide unequally at every ladder node until such switching transition is completed and proper ladder node current can be re-established. Consequently, the digital-to-analog converter of the type shown in the von Sichart et. al. patent will exhibit voltage coefficient of resistance and switching asymmetry, thereby adversely affecting digital-to-analog conversions, accuracy and linearity.